The algorithm was first written and debugged in Turbo Pascal on a Z80.
Then the Pascal programm was divided into states so that at most
one data and one address transaction were done in parallel. The
resulting state machine was rewritten for CUPL on a VAX11, translated,
simulated, optimized and sliced to many PALS by CUPL. Barring one wire wrap error, the board worked right away.
One of the first 80386 computer boards in Multibus II format.
Features CPU, floating point coprocessor, cache, Multibus II message passing coprocessor,
a whopping 8 MB of RAM, com1:, com2:, lpt1:, floppy, SCSI and an Inmos Transputer link.
The board has suffered a bit in the meantime.
The first thing I did after graduation was the construction of a
signal averager. It took 8 Schottky TTL computation units in parallel to get the the
done in real time. The brown board fed the computation units and collected the results.
The ADC was a TRW 8 bit 20 MHz flash converter, which was quite an achievement at
that time. It is the large black bar with the white dot in the lower right
of the blurred
part of the picture. The ADC chip was huge, the reference ladder
was visible to the naked eye. We were given an extra chip in a resin
The signal averager took two thirds of a 6HU 19" crate.
5 years later I did a redesign in 100K ECL that needed only two
computation units for a 8 Bit / 100 MHz real time digitizer. That one
was huge and hot.
Another 5 years later I condensed everything into a single 100 * 220 mm Eurocard.
The pipeline of the computation core was 13 clocks deep. ADC rate was 200 MHz.
Those Siemens pipelined demultiplexing ECL to TTL converters were heaven sent.
They happened to be like custom made for us.
I did the whole project : analog, digital, FPGAs, board layout, soldering and software driver.
Mezzanine controller board featuring 56002 digital signal processor
Two channel logarithmic 2nd IF amplifier, phase comparator and
phase / amplitude digitizer for a 1-1000 MHZ Poynting Vector analyzer.
This had to be extremely small so that the analyzer probe would not disturb the field to be measured.
Two bandwidths suitable for EMC measurements are provided.
The Phase comparator and ADCs for amplitude 1, amplitude 2 and phase are on the back side.
Total gain is > 100 dB but it does not oscillate, even with these "sociable" inductors and shielding removed.
Size is 55 * 55 mm
Controller, synthesized local oscillator and second oscillator for the same Poynting vector analyzer.
The local oscillator is tuneable from 900 MHz to 2200 MHz in sub-Hz steps. It uses a Qualcom PLL
circuit to multiply a filtered DDS-generated reference frequency. The DDS is fed from a ~120 MHz
Butler crystal oscillator.
The second oscillator multiplies the 120 MHz crystal oscillator to 1080 MHz.
The controller runs on a subharmonic of the crystal with accurate baud rates.
Two boards, 55 * 55 mm each.
I have done the whole project: Concept, design, layout & software.
868 MHz data transceiver based on TI TRF6900A
Large Virtex-2E and a Coolrunner for an ultrasonics pipeline pig.
Pipeline pigs look like a cross of a torpedo and a jelly fish. They are
pumped together with the oil / gas through a pipeline
and on their journey of a few hundred miles they check the pipeline for defects with ultrasonics. Typically, there are
1024 ultrasonic heads distributed across the tube periphery.
The bottom side of this board isn't empty, either. Power dissipation
was a great problem because the system contains lots of these
The board is conduction cooled. In addition to the many routing layers it contains thick copper planes
that transport the heat to the periphery. It is clamped to the chassis with wedge locks.
The chassis is made from machined aluminium and is soldered in a salt bath.
Forced air cooling would have required more power for the fans than for the electronics because of mechanical constraints.
Board material is Polyimide, because FR4/FR5 would soak
hydrocarbon and swell if the enclosure was not absolutely
Pipelines are hostile. We got connectors to the outer world from a submarine supplier.
2003 to 2005 I was a member of the team that designed these 10 GBit/s XFP fiber optics transceivers
(and XPAK / XAUI, too )
The Lab View
My own lab, from DC to > 20 GHz.